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24-Bit, 192kHz Stereo ADC
DESCRIPTION
The WM8785 is a stereo audio ADC with differential inputs designed for high performance recordable media applications. Data is provided as a PCM output. Stereo 24-bit multi-bit sigma-delta ADCs are used with digital audio output word lengths of 16 to 32 bits, and sampling rates from 8kHz to 192kHz. The device has a selectable high pass filter to remove residual DC offsets. The device also supports a TDM bus for data out. The device is controlled via a 2 or 3 wire serial interface. The interface provides access to all features including oversampling rate, audio format, powerdown, master/slave control and digital signal manipulation. The device is supplied in a 20-lead SSOP package.
WM8785
FEATURES
* * * * * * * * * SNR 111dB (`A' weighted @ 48kHz) THD -102dB (at -0.1dB) Sampling Frequency: 8 - 192kHz 2 or 3 Wire Microprocessor Control Interface Master or Slave Clocking Mode Programmable Audio Data Interface Modes - I2S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths A TDM bus is supported for data out Supply Voltages - Analogue 4.5 to 5.5V - Digital core: 2.7V to 3.6V 20-lead SSOP package
APPLICATIONS
* * * * Recordable DVD Players Personal Video Recorders High End Sound Cards Studio Audio Processing Equipment
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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Production Data, December 2006, Rev 4.1
Copyright (c)2006 Wolfson Microelectronics plc
WM8785 TABLE OF CONTENTS
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DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY ............................................................................................................ 7
SIGNAL TIMING REQUIREMENTS .......................................................................8
SYSTEM CLOCK TIMING ............................................................................................. 8 AUDIO INTERFACE TIMING - MASTER MODE, PCM DATA ...................................... 8 AUDIO INTERFACE TIMING - SLAVE MODE, PCM DATA ......................................... 9 CONTROL INTERFACE TIMING - 3-WIRE MODE ...................................................... 9 CONTROL INTERFACE TIMING - 2-WIRE MODE .................................................... 10 POWER-ON RESET ................................................................................................... 11
DIGITAL FILTER CHARACTERISTICS ...............................................................12
TERMINOLOGY .......................................................................................................... 12
FILTER RESPONSES ..........................................................................................13 DEVICE DESCRIPTION.......................................................................................16
INTRODUCTION ......................................................................................................... 16 DIGITAL AUDIO INTERFACE ..................................................................................... 16 DIGITAL HIGH PASS .................................................................................................. 20 DATA OUT PIN DISABLE ........................................................................................... 21 CONTROL INTERFACE.............................................................................................. 21 TIME DIVISION MULTIPLEXED DATA OUT............................................................... 22 TDM SELECTION ....................................................................................................... 23 OVERSAMPLING RATIOS AND SIGMA-DELTA MODULATOR FREQUENCY.......... 26 MASTER CLOCK AND AUDIO SAMPLE RATES........................................................ 26 MLCK AND LRCLK PHASE RELATIONSHIP.............................................................. 27 POWER DOWN CONTROL ........................................................................................ 27 REGISTER MAP ......................................................................................................... 28
APPLICATIONS INFORMATION .........................................................................29
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 29
PACKAGE DIMENSIONS ....................................................................................30 IMPORTANT NOTICE ..........................................................................................31
ADDRESS: .................................................................................................................. 31
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WM8785
PIN CONFIGURATION
AINL+ AINLVREFGND AVDD AGND LRCLK DOUT BCLK MCLK NC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AINR+ AINRVREF VMID DGND DVDD NC CSB SDIN SCLK
ORDERING INFORMATION
ORDER CODE WM8785GEDS/V WM8785GEDS/RV Note: Reel quantity = 2,000 TEMPERATURE RANGE -25C to +85C -25C to +85C PACKAGE 20-lead SSOP (Pb-free) 20-lead SSOP (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PEAK SOLDERING TEMPERATURE 260oC 260oC
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WM8785 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME AINL+ AINLVREFGND AVDD AGND LRCLK DOUT BCLK MCLK NC SCLK SDIN CSB NC DVDD DGND VMID VREF AINRAINR+ TYPE Analogue Input Analogue Input Analogue Reference Supply Supply Digital Input / Output Digital Output Digital Input / Output Digital Input NC Digital Input Digital Input / Output Digital Input NC Supply Supply Analogue Output Analogue Reference Analogue Input Analogue Input Left Channel Positive Input Left Channel Negative Input Negative Reference Connection Analogue Supply Analogue Ground (return path for AVDD) Audio Interface Left / Right Clock ADC Digital Audio Data Audio Interface Bit Clock Master Clock No Connection Control Interface Clock Input / 2 wire output Control Interface Data Input DESCRIPTION
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Chip Select / Control Interface Format Selection / 3 wire address select No connection Digital Supply Digital Ground (return path for DVDD) Midrail Voltage Decoupling Capacitor Reference Voltage Decoupling Capacitor Right Channel Negative Input Right Channel Positive Input
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WM8785
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency Operating temperature range, TA Storage temperature after soldering Note: Analogue and digital grounds must always be within 0.3V of each other. -25C -65C MIN -0.3V -0.3V DGND -0.3V AGND -0.3V MAX +3.63V +7V DVDD + 0.3V AVDD +0.3V 40MHz +85C +150C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Ground SYMBOL DVDD AVDD DGND,AGND TEST CONDITIONS MIN 2.7 4.5 0 TYP MAX 3.6 5.5 UNIT V V V
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WM8785 ELECTRICAL CHARACTERISTICS
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Test Conditions DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode unless otherwise stated. PARAMETER ADC Performance Full Scale Input Signal Level (for ADC 0dB Input) Input resistance Input capacitance Signal to Noise Ratio (Note 1,2,4) SNR A-weighted, @ fs = 48kHz Unweighted, @ fs = 48kHz Signal to Noise Ratio (Note 1,2,4) SNR A-weighted, @ fs = 96kHz Unweighted, @ fs = 96kHz Signal to Noise Ratio (Note 1,2,4) SNR A-weighted, @ fs = 192kHz Unweighted, @ fs = 192kHz Total Harmonic Distortion THD 1kHz, -0.1dB Full Scale @ fs = 48kHz 1kHz, -0.1dB Full Scale @ fs = 96kHz 1kHz, -0.1dB Full Scale @ fs = 192kHz Total Harmonic Distortion THD 1kHz, -0.1dB Full Scale @ fs = 48kHz 1kHz, -0.1dB Full Scale @ fs = 96kHz 1kHz, -0.1dB Full Scale @ fs = 192kHz Dynamic Range Channel Level Matching Power Supply Rejection Ratio PSRR DNR -60dBFS 20kHz signal 1kHz 100mVpp, applied to AVDD, DVDD 20Hz to 20kHz 100mVpp Digital Logic Levels (CMOS Levels) Input LOW level Input HIGH level Input leakage current Input capacitance Output LOW Output HIGH Analogue Reference Levels Midrail Reference Voltage Potential Divider Resistance Buffered Reference Voltage VMID RVMID VREF AVDD to VMID and VMID to VREFGND AVDD to VMID and VMID to GND -3% -3% AVDD/2 50 0.8 x AVDD +3% +3% V k V VOL VOH IOL=1mA IOH= -1mA 0.9 x DVDD VIL VIH 0.7 x DVDD -1 0.2 5 0.1 x DVDD +1 0.3 x DVDD V V A pF V V 102 102 2.0 10 10 111 108 111 108 111 108 -102 -102 -102 0.0008 0.0008 0.0008 111 0.1 50 45 0.0025 -92 Vrms k pF dB dB dB dB dB dB dB dB dB % % % dB dB dB dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
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WM8785
Test Conditions DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode unless otherwise stated. PARAMETER Supply Current Analogue supply current Digital supply current Power Down Note: 1. VMID is decoupled with 10uF and 0.1uF capacitors close to the device package. Smaller capacitors may reduce performance. 27 5 22 mA mA uA SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
TERMINOLOGY
1. Signal-to-noise ratio (dB) - Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, over a 20Hz to 20kHz bandwidth. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. All performance measurements are done with a 20kHz low pass filter, and where noted an A-weight filter, except where noted. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although this is not audible, it may affect dynamic specification values
2.
3. 4. 5.
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WM8785 SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
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Figure 1 System Clock Timing Requirements Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock cycle time MCLK duty cycle TMCLKY TMCLKDS 25 60:40 40:60 ns SYMBOL MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - MASTER MODE, PCM DATA
Figure 2 Digital Audio Data Timing - Master Mode (see Control Interface) Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information LRCLK propagation delay from BCLK falling edge DOUT propagation delay from BCLK falling edge tDL tDDA 0 0 10 11 ns ns SYMBOL MIN TYP MAX UNIT
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WM8785
AUDIO INTERFACE TIMING - SLAVE MODE, PCM DATA
Figure 3 Digital Audio Data Timing - Slave Mode Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK cycle time LRCLK set-up time to BCLK rising edge LRCLK hold time from BCLK rising edge DOUT propagation delay from BCLK falling edge tBCY tLRSU tLRH tDD 25 10 10 0 11 ns ns ns ns SYMBOL MIN TYP MAX UNIT
CONTROL INTERFACE TIMING - 3-WIRE MODE
tCSL CSB tCSS tSCL tSCS tCSH
tSCY tSCH SCLK
SDIN tDSU tDHO
LSB
Figure 4 Control Interface Timing - 3-Wire Serial Control Mode Test Conditions DVDD = 3.3V, DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising Pulse width of spikes that will be suppressed tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tps 80 200 80 80 40 40 40 40 40 4 6 ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8785
CONTROL INTERFACE TIMING - 2-WIRE MODE
t3 SDIN t4 t6 SCLK t1 t9 t7 t2 t5 t3
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t8
Figure 5 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions DVDD = 3.3V, DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 4 600 900 6 0 80 80 600 600 100 300 300 5 MHz ns us ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8785
POWER-ON RESET
The WM8785 has an internal power-on reset circuit. The reset sequence is entered at power-on or power-up (DVDD). Until the internal reset is removed, DOUT is forced to zero. DOUT remains zero for a count equal to 32 sample clocks, after power up. (This count is driven by MCLK and is independent of any external LRCLK).
Figure 6 POR Circuit
Figure 7 POR Timing
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WM8785 DIGITAL FILTER CHARACTERISTICS
The WM8785 digital filter characteristics scale with sample rate.
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PARAMETER Passband Passband Ripple Stopband Stopband Attenuation Group Delay
TEST CONDITIONS +/- 0.005dB -6dB
MIN 0
TYP
MAX 0.454fs
UNIT
ADC Sample Rate (Single Rate - 48KHz typically) 0.5fs +/- 0.005 0.546fs f > 0.546fs -85 32/fs +/- 0.005dB -6dB Passband Ripple Stopband Stopband Attenuation Group Delay ADC Sample Rate (Quad Rate - 192kHz typically) Passband +/- 0.005dB -3dB -6dB Passband Ripple Stopband Stopband Attenuation Group Delay High Pass Filter Corner Frequency -3dB -0.5dB -0.1dB f > 0.75fs 0.75fs -85 10/fs 3.7 10.4 21.6 dB s Hz 0 0.45fs 0.5fs +/- 0.005 dB 0.25fs f > 0.546fs 0.546fs -85 32/fs dB s 0 0.5fs +/- 0.005 dB 0.454fs dB s dB
ADC Sample Rate (Dual Rate - 96kHz typically) Passband
TERMINOLOGY
1. 2. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple - any variation of the frequency response in the pass-band region
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WM8785
FILTER RESPONSES
SINGLE RATE 48k
0 -20 Response (dB) -40 -60 -80 -100 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (Fs)
Figure 8 Single Rate 48k Filter Response
0 -20 Response (dB)
-40
-60 -80
-100 0.4 0.45 0.5 Frequency (Fs) 0.55 0.6
Figure 9 Single Rate 48k Filter Response
0.15 0.1 Response (dB) 0.05 0 -0.05 -0.1 -0.15 0 0.1 0.2 Frequency (Fs)
Figure 10 Single Rate 48k Filter Response
0.3
0.4
0.5
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DUAL RATE 96k
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0 -20 Response (dB) -40 -60 -80 -100 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (Fs)
Figure 11 Dual Rate 96k Filter Response
0 -20 Response (dB)
-40
-60 -80
-100 0.4 0.45 0.5 Frequency (Fs) 0.55 0.6
Figure 12 Dual Rate 96k Filter Response
0.15 0.1 Response (dB) 0.05 0 -0.05 -0.1 -0.15 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5
Figure 13 Dual Rate 96k Filter Response
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QUAD RATE 192k
0 -20 Response (dB) -40 -60 -80 -100 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (Fs)
Figure 14 Quad Rate 192k Filter Response
0 -20 Response (dB)
-40
-60 -80
-100 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (Fs)
Figure 15 Quad Rate 192k Filter Response
-2.5 -2.6 -2.7 -2.8 Response (dB) -2.9 -3 -3.1 -3.2 -3.3 -3.4 -3.5 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5
Figure 16 Quad Rate 192k Filter Response
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WM8785 DEVICE DESCRIPTION
INTRODUCTION
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The WM8785 is a high performance stereo audio ADC designed for demanding recording applications such as DVD recorders, studio mixers, PVRs, and AV amplifiers. The WM8785 consists of stereo line level inputs, followed by a sigma-delta modulator and digital filtering. The WM8785 uses a multi-bit high-order oversampling architecture delivering high SNR operating at oversampling ratios from 128fs to 32fs according to the sample rate. Sample rates from 8kHz to 192kHz are supported. The WM8785 supports master clock rates from 128fs to 768fs. The digital filter is a high performance linear phase FIR filter. The digital filters are optimised for each sample rate. Also included is a selectable high pass filter to remove residual DC offsets from the input signal. The output from the ADC is available on a configurable digital audio interface. It supports a number of audio data formats including I2S, Left justified and Right justified or DSP, and can operate in master or slave modes. The WM8785 can be controlled through a 2 wire or 3 wire MPU control interface. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. A TDM bus is supported for multiplexing data output. The WM8785 can be powered down under software control to reduce system power consumption.
DIGITAL AUDIO INTERFACE
The digital audio interface uses three pins: * * * DOUT: ADC data output LRCLK: ADC data alignment clock BCLK: Bit clock, for synchronisation
The digital audio interface takes the data from the internal ADC digital filters and places it on DOUT and LRCLK. DOUT is the formatted digital audio data stream output from the ADC digital filters with left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left or Right channel data is present on the DOUT line. DOUT and LRCLK are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low transition. DOUT is always an output. BCLK and LRCLK maybe inputs or outputs depending whether the device is in Master or Slave mode, (see Master and Slave Mode Operation, below). Four different audio data formats are supported: * * * * Left justified Right justified I 2S DSP
They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8785 can be configured as either a master or slave mode device. As a master device the WM8785 generates BCLK and LRCLK and thus controls sequencing of the data transfer on DOUT. In slave mode, the WM8785 responds with data to clocks it receives over the digital audio interface. The mode can be selected by setting MCR=000 (see Table below). Master and slave modes are illustrated below.
Figure 17a Master Mode
Figure 17b Slave Mode PD Rev 4.1 December 2006 16
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AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 18 Left Justified Audio Interface (assuming n-bit word length) In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 19 Right Justified Audio Interface (assuming n-bit word length) In I S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
2
Figure 20 I2S Justified Audio Interface (assuming n-bit word length)
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WM8785
Production Data In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output will resemble the frame pulse shown in Figure 21 and Figure 22. In device slave mode, Figure 23 and Figure 24, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse.
Figure 21 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)
Figure 22 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master)
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Figure 23 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)
Figure 24 DSP/PCM Mode Audio Interface (mode B, LRP=1, Slave)
AUDIO INTERFACE CONTROL
The register bits controlling the audio interface are summarised below. Note that dynamically changing the software format may cause erroneous operation of the interfaces and is therefore not recommended. All ADC data is 2's complement. The length of the digital audio data is programmable at 16/20/24 or 32 bits, as shown below. The ADC digital filters process data using 24 bits. If the WM8785 is programmed to output 16 or 20 bit data then it strips the LSBs from the 24 bit data. If the device is programmed to output 32 bits then it packs the LSBs with zeros. In master mode LRCLK and BCLK are generated on chip. In slave mode they are received from an external source.
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WM8785
REGISTER ADDRESS R0 (00h) Sample Rate and Digital Audio Interface Format BIT 6:5 LABEL FORMAT DEFAULT 10 DESCRIPTION Audio Data Format Select 11: DSP Format 10: I2S Format 01: Left justified 00: Right justified Audio Data Word Length 11: 32 bits (see Note) 10: 24 bits 01: 20 bits 00: 16 bits right, left and I S modes - LRCLK polarity 1 = invert LRCLK polarity 0 = normal LRCLK polarity
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R1 (01h) Digital Audio Interface Format and TDM
1:0
WL
10
2
LRP
0
DSP Mode - A/B select 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 3 BCLKINV 0 BCLK invert bit (for master and slave modes) 0 = BCLK not inverted 1 = BCLK inverted Left/Right channel swap 1 = swap left and right DAC data in audio interface 0 = output left and right data as normal
4
LRSWAP
0
Table 1 Audio Data Format Control Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual word length is 24 bits.
DIGITAL HIGH PASS
The high pass filter can be enabled using the HPFL and HPFR bits (see digital filter characteristics) REGISTER ADDRESS R2(02h) HPfilter , Output disable, Power down, Mono mode BIT 0 LABEL HPFR 1 DEFAULT DESCRIPTION Digital High Pass Filter, Right Channel 0 = HPF Off 1 = HPF On Digital High Pass Filter, Left Channel 0 = HPF Off 1 = HPF On
1
HPFL
1
Table 2 Oversampling Ratio Selection The high pass filter should only be disabled for procedures such as DC offset calibration. It should be noted that the output range of the ADC with a DC level applied and HPF disabled is as follows: Maximum code: 7FDFB0 Minimum code: 802033
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DATA OUT PIN DISABLE
To prevent any communication problems on the Audio Interface, the interface can be disabled (DOUT tristated and floating) using the SDODIS bit. REGISTER ADDRESS R2(02h) HP Filter , Output disable, Power down, Mono mode BIT 2 LABEL SDODIS 0 DEFAULT DESCRIPTION DOUT serial data pin disable 0 = DOUT pin enabled 1 = DOUT pin off (high impedance)
Table 3 Oversampling Ratio Selection
CONTROL INTERFACE
SELECTION OF CONTROL MODE
The WM8785 is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each control register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The CSB pin is sampled at power-up and selects the interface format. After power-up the pin is available to latch in control data in 3-wire interface mode.
Figure 25 Control Interface Mode Selection CSB PIN STATUS Low High INTERFACE FORMAT 2 wire 3 wire
Table 4 Control Interface Mode Selection
SETUP/HOLD tpusetup tpuhold
TIME 250us 250us
Table 5 Control Interface Mode Selection
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3-WIRE SERIAL CONTROL MODE
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In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB latches in a complete control word consisting of the last 16 bits.
latch CSB
SCLK
SDIN
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
control register address
control register data bits
Figure 26 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8785 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the WM8785). The WM8785 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8785 and the R/W bit is `0', indicating a write, then the WM8785 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is `1', the WM8785 returns to the idle condition and wait for a new start condition and valid address. Once the WM8785 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8785 register address plus the first bit of register data). The WM8785 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8785 acknowledges again by pulling SDIN low. The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high. After receiving a complete address and data sequence the WM8785 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
SDIN
DEVICE ADDRESS (7 BITS)
RD / WR BIT
ACK (LOW)
CONTROL BYTE 1 (BITS 15 TO 8)
ACK (LOW)
CONTROL BYTE 1 (BITS 15 TO 8)
ACK (LOW)
SCLK
START
register address and 1st register data bit
remaining 8 bits of register data
STOP
Figure 27 2-Wire Serial Control Interface The WM8785 device address is 0011010.
TIME DIVISION MULTIPLEXED DATA OUT
The WM8785 can be used to time division multiplex several data channels at once. For example, the diagram below illustrates 4 devices connected to the same TDM bus. While one DOUT pin is driving data, the others will be tri-stated.
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Figure 28 WM8785 in Time Division Multiplexing Setup
Note: 1. 2. TDM is only available in slave mode. Right justified mode is not supported
TDM SELECTION
The figure below indicates how data is multiplexed onto the TDM bus, in left justified mode. This assumes we have 4 devices, and each device has 2 data channels: * * LCHAN = left channel RCHAN = right channel
Each channel is allocated 32 BCLKs
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Figure 29 WM8785 in Time Division Multiplexing Left Justified Mode
Up to 4 devices (8 channels) can be supported, which would require 256 BCLKs per sample. (whereas 128 BCLKs will allow only 2 devices, or 4 channels). The table below shows the range of BCLK frequencies required.
BCLK RATE 64 fs 128 fs 192 fs 256 fs
DEVICES THAT CAN BE SUPPORTED 1 1, 2 1, 2 1, 2, 3, 4
OVER-SAMPLE RATIOS SUPPORTED (SET BY OSR) Single/dual/quad rates all supported
Single rate only supported
Table 6 Range of BCLK Frequencies Required Note: MCLK frequency must always be greater or equal to BCLK frequency To avoid bus contention all chips on the TDM should be programmed before DOUT is released after power up (DOUT is held at vss for 32 samples after power-up). Alternatively SDODIS should be set while devices are programmed (to tri-state DOUT).
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Production Data Two registers must be set to enter TDM mode: * * DEVNO[2:0] sets the number of devices which are on the bus TDM[2:0] allocates a TDM slot to the device
WM8785
REGISTER ADDRESS R1(h01) Clocking, Sample Rates, Oversampling and Signal Control
BIT 7:5
LABEL DEVNO[2:0]
DEFAULT 000
DESCRIPTION Number of TDM Devices 000 = 1 Device 001 = 2 Devices 010 = 3 Devices 011 = 4 Devices
Table 7 DEVNO
REGISTER ADDRESS R2(h02) Clocking, Sample Rates, Oversampling and Signal Control
BIT 8:6
LABEL TDM[2:0]
DEFAULT 000
DESCRIPTION Time Division Multiplexing Device Select 000 = Device 0 (no delay) 001 = Device 1 (64 BCLK delay) 010 = Device 2 (128 BCLK delay) 011 = Device 3 (192 BCLK delay)
Table 8 TDM
Note: When TDM is not required, the register will default to 000 (normal operation) The figures below indicate TDM mode for I2S and DSP mode A.
Figure 30 TDM Bus I2S Mode
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WM8785
OVERSAMPLING RATIOS AND SIGMA-DELTA MODULATOR FREQUENCY
Production Data
For correct operation of the device and optimal performance, the user must select the appropriate ADC modulator oversampling ratio. The oversampling ratio is selected using the OSR[1:0] bits. REGISTER ADDRESS R0(h00) Signal Control BIT 4:3 LABEL OSR[1:0] 00 DEFAULT DESCRIPTION Oversampling Ratio Control 00: Single Rate (128fs) 01: Dual Rate (64fs) 10: Quad Rate (32fs) 11: Not Valid
Table 9 Oversampling Ratio Selection
The WM8785 can operate at sample rates from 8kHz to 192kHz. The WM8785 uses a sigma-delta modulator that operates at frequencies between 1.024MHz and 6.144MHz SAMPLING RATE (LRCLK) 8kHz 32kHz 44.1kHz 48kHz 96kHz 192kHz OVERSAMPLING RATIO SIGMA-DELTA MODULATOR FREQUENCY (MHZ) 1.024 4.096 5.6448 6.144 6.144 6.144
Single Rate (128fs) Single Rate (128fs) Single Rate (128fs) Single Rate (128fs) Dual Rate (64fs) Quad Rate (32fs)
Table 10 Sigma-delta Modulator Frequency
MASTER CLOCK AND AUDIO SAMPLE RATES
Master clock frequencies of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs are supported. In slave mode the WM8785 automatically detects the audio sample rate. In Master mode the master clock frequency is selected using MCR[2:0] bits. This is described in table below. REGISTER ADDRESS R0(h00) Clocking, Sample Rates, BIT 2:0 LABEL MCR[2:0] DEFAULT 000 DESCRIPTION Master/Slave Selection 000: Slave Mode 001: Master Mode, 128fs 010: Master Mode, 192fs 011: Master Mode, 256fs 100: Master Mode, 384fs 101: Master Mode, 512fs 110: Master Mode, 768fs
Table 11 Master Clock Frequency The master clock (MCLK) is used to operate the digital filters and the noise shaping circuits. The WM8785 supports a wide range of master clock frequencies, and can generate many commonly used audio sample rates directly from the master clock. Table 1 shows the recommended master clock frequencies for different sample rates
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Production Data
WM8785
OVERSAMPLING RATIO Single Rate Single Rate Single Rate Dual Rate Quad Rate MASTER CLOCK FREQUENCY (MHZ) 128fs 24.576 192fs 36.864 256fs 8.192 11.2896 12.288 24.576 384fs 12.288 16.9344 18.432 36.864 512fs 16.384 22.5792 24.576 768fs 24.576 33.8688 36.864 -
SAMPLING RATE (LRCLK) 32kHz 44.1kHz 48kHz 96kHz 192kHz
Table 12 Slave Mode: Recommended Master Clock Frequency Selection
MLCK AND LRCLK PHASE RELATIONSHIP
The WM8785 does not require a specific phase relationship between MLCK and LRCLK. If the relationship between MCLK and LRCLK changes by more than +/-8 BCLKs in a 64 BLCK frame, the WM8785 will attempt to re-synchronise. During re-synchronisation, data samples may be dropped or duplicated.
POWER DOWN CONTROL
The WM8785 can be powered down by setting the PWRDNL and PWRDNR bits. This is described in the table below. REGISTER ADDRESS R2(02h) Signal control BIT 3 LABEL PWRDNR 0 DEFAULT DESCRIPTION Power Down Right Channel 0 = Power On 1 = Power Off Power Down Left Channel 0 = Power On 1 = Power Off
4
PWRDNL
0
Table 13 Power Down Control
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WM8785
REGISTER MAP
REGISTER ADDRESS REMARK BIT8 BIT7 BIT6 BIT5 R0(00h) 00_0000 Sample Rate And Audio IF Format Audio IF Format And TDM Signal Control Reset 0 0 FORMAT BIT4 OSR BIT3 BIT2 MCR BIT1 BIT0
Production Data
DEFAULT 0_0000_0011
R1(01h)
00_0001
0
DEVNO
LRSWP
BCLKINV
LRP
WL
0_0000_1010
R2(02h) R7(07h)
00_0010 00_0111
TDM
0
PWRDNL
PWRDNR
SDODIS
HPFL
HPFR
0_0000_0011 0_0000_0000
Writing to reg 7 will cause software reset
Table 14 Register Map for Control Interface Notes:
1. 2. 3. 4. 5.
All unused register bits should be set to zero The interface will initiate SWRB whenever R7 is addressed, regardless of the data input. SWRB is released on the next register write or after 4 MCLK cycles (which ever occurs first). Until the SWRB is released, DOUT is forced to zero. DOUT remains zero for a count of 32 sample clocks SWRB is released, this count is driven by MCLK and is independent of any external LRCLK.
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Production Data
WM8785
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Notes: 1. 2. 3. 4. AGND and DGND should be connected as close to the WM8785 as possible. C1 to C6 should be placed as close to the WM8785 device as possible. Capacitor types should be chosen carefully. Capacitors with very low ESR are recommended for optimum performance, such as X7R. VMID and VREF decoupling capacitors must be high quality electrolytic capacitors to achieve datasheet performance; ceramic capacitors are not acceptable. An active input filter is required to achieve datasheet performance. The circuit shown is a tested inverting reference example.
Figure 31 External Component Diagram
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WM8785 PACKAGE DIMENSIONS
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
Production Data
DM0015.C
b
20
e
11
E1
E
1
10
GAUGE PLANE
D
A A2
A1 -C0.10 C
SEATING PLANE
c
L L1
0.25
Symbols A A1 A2 b c D e E E1 L L1 REF: MIN ----0.05 1.65 0.22 0.09 6.90 7.40 5.00 0.55 0
o
Dimensions (mm) NOM --------1.75 0.30 ----7.20 0.65 BSC 7.80 5.30 0.75 1.25 REF o 4 JEDEC.95, MO -150
MAX 2.0 ----1.85 0.38 0.25 7.50 8.20 5.60 0.95 8
o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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Production Data
WM8785
IMPORTANT NOTICE
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